The main aim of this project is to design a 1-bit serial adder, simulate its functionality and obtain a layout on silicon, using the 0.35µ process from AMS. The circuit designed shows a working serial adder clocking at (100MHz of nsecs) with a delay of 0.56910nsec. The area of the layout is 99.30×16.35 µm2 in this technology. The circuit performs an 8-bit addition in 0.56910×8 nsesc. The circuit uses a standard 1-bit full adder and it has a feedback loop using a D-flip-flop in order to transmit the carry bit to the next input value. The final layout product has 3-input pads and 2-output pads, with power and ground pads.
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The process known as serial addition of binary numbers is well known in the computing and units capable of performing such serial binary addition ordinarily comprise a basic portion of more complex computation devices. In the past, such serial adders for binary numbers have employed vacuum tube circuitry for the most part and have accordingly been subject to the disadvantages that they are relatively in large size, fragile in configuration and are subject to operating failures. These factors raise serious questions of disposition of components and problems of maintenance. The present invention serves to obviate the foregoing difficulties and in essence provides a serial adder structure capable of performing full addition of binary numbers. It is accordingly an object of the present invention to provide an improved serial adder for use in computing applications.
An object of the present invention resides in the provision of an improved serial adder for binary digital applications employing magnetic amplifiers as components thereof. Another object of the present invention is the provision of the serial adder for binary numbers which adders can be made in relatively smaller sizes. A still further object of the present invention resides in the provision of a computation device comprising, in combination, a plurality of magnetic amplifiers and a plurality of gating devices so interconnected with one another that the mathematical process known as a serial bit addition. The binary adder of the present invention includes provision for selective coupling the input train pulses to be added as well as carry pulses produced by the device itself to the plurality of gates, and the gates are adapted by themselves to selectively pass signal pulses required for the operation or inhibition of the plurality of magnetic amplifiers mentioned above. In digital systems, digital signal processing and control systems we can control it when we are able to count. Addition is the fundamental operation for all these systems.
The fastness and accuracy are highly influenced by the adders we are use for the circuit design. Adders are very important components in the digital components because of their extensive use in digital operations such as multiplication, subtraction and division. The execution of binary operations inside a circuit would be greatly advanced by improving the performance of the digital adders. The main aim of designing the bit serial adder is to
Perform one bit at a time, using the first bit operation results to influence the processing of subsequent bits. It reduces the amount of hardware required as it passes all the bits in the same logic. However this approach needs 1/nth part of hardware when compared to the n-bit parallel adders. As we are using 1-bit instead of n-bits its structure reduces the signal routing and performs at high speed as we are using 1bit register for the temporary storage and one full adder rather than an n-bit adder. The reduction in the price of the logic results in taking n clock cycles to execute this serial hardware, whereas parallel hardware executes in one clock cycle. This bit structure deals with the bit stream hence this have been successfully used in many applications like digital systems, digital signal processing, control systems etc. It was extremely popular in 2-5u technology range. The performance of a digital circuit block is gauged by analysing its power dissipation, layout area and its operating speed.
The main aim of this project is to design a 1-bit serial adder. Through this project research we get the knowledge of working behaviour and performance of the 1-bit serial adder. Adders are the basic components for the designing of any digital circuit. Adders are very important components in the digital components because of their extensive use in digital operations such as multiplication, subtraction and division. The execution of binary operations inside a circuit would be greatly advanced by improving the performance of the digital adders. The main aim of designing the bit serial adder is to perform one bit at a time, using the first bit operation results to influence the processing of subsequent bits. Here in this case the one bit serial adder is designed by using a flip-flop and full adder. .
This circuit has two stages full adder stage for the addition of two bits that are entered serially and second stage is flip-flop stage which temporarily stores the carry until the next stage is processed. The temporary storage of the carry in the flip-flop depends on the clock pulse. Its design principle shows how the two inputs entered serially. These two inputs will be added by the full adder along with the carry which was temporarily stored by the flip-flop and gives us the sum output and carry output. The normal 1-bit serial adder uses the XOR gates from the available core library. But in this XOR gate there is an OR gate which usually reduces the performance of the XOR gate. Hence the circuit has been modified by designing the XOR gate by using the NAND gates.
What we would like to do now is find the easy way to use the sub tractor along with the serial adder circuit. By using this sub tractor we can subtract the lower bit value from higher value.
This binary sub tractor has been added to one of the input which we are thinking to subtract the value. In our serial adder circuit the sub tractor is attached to the one of the inputs Y which is usually a XOR gate. This results in the subtraction of Y value from higher bit values.
BACKGROUND
2.1 Addition:
Addition is a process of adding bits. Binary addition means adding binary bits 0’s and 1’s and sum and carry generated in binary farm in any signal processing. Now lets consider the 4-bit addition example,
As shown above A and B bits added giving Sum out by rippling the carry at each stage and C4 as final carry obtained.
2.2 Subtraction:
Subtraction is a process of adding a positive bit to the negative bit. Negative of a bit means 2’s compliment of it. This is nothing but adding 1 bit to LSB of its 1’s compliment. 1’s compliment is nothing but reversing the logic of the bits. Now lets consider the 4-bit subtraction example,
The above subtraction technique dedicated to the subtracting a smaller binary from a larger binary. If it changes it just followed by few more steps as change sign bit (MSB) to zero, then change it to its 2’s compliment as before process.
Metal-Oxide-Silicon Field-Effect transistors (Mosfet’s)
NMOS Transistor
Here is a diagram of nmos transistor
The source and drain are connected to the two blobs of n-type semiconductor material. The
gate is on top, separated (and electrically insulated) from the rest of the transistor by a thin layer of silicon dioxide (same material as sand — doesn’t conduct at all). The source and drain are separated by p-type material. This forms two diodes pointed in opposite directions (when you have n-type next to p-type material, you get a diode), so no current can flow between the source and drain. When a high voltage (higher than the voltage level of the source, which is defined as the lower voltage of the two end terminals) is applied to the gate, it puts a positive charge on the gate. This attracts a negative charge in the region underneath the gate (opposite charges attract), forming a “channel of negative charge carriers” or an n-channel between the source and drain, which allows current to flow. So the nMOS transistor conducts when the gate is raised to the high voltage level, which we consider to be the logic level for 1 (true).
PMOS TRANSISTOR
The pMOS transistor is the dual of the nMOS transistor. You can look at the same diagram, but swap every n and p, and every + and -. Now, when the voltage at the gate is lower than the source (the higher voltage of the two end terminals for a pMOS transistor), we end up with a negative charge on the gate, which induces a positive channel underneath the gate, which allows current to flow. So the pMOS transistor conducts when the gate voltage is low, which we consider to be the logic level for 0 (false).
The full names of what is being described are “enhancement mode n-channel or p-channel metal-oxide semiconductor field effect transistors (MOSFET)”. “Enhancement mode” refers to the fact that we have to create the channel by applying voltage to the gate. (There are also “depletion mode” transistors that have a channel built in to start with.) “Field effect” refers to the fact that we’re using the electric field from the charge at the gate to control things. “Metal-oxide semiconductor” refers to the fact that we’re using an oxide to insulate the gate from the rest of the transistor. The two types of transistors are named for the channel: nMOS has an n-channel; pMOS has a p-channel.
Cmos
There are many ways to make logic gates (not to be confused with the gate of the transistor) out of transistors. What I’m showing here is the dominant way that gates are done in digital electronics today, but there are many variations out there. This is called “static CMOS logic”. “Static” refers to the fact that there are not clocks involved. “CMOS” stands for “complementary metal-oxide semiconductor”. The “complementary” means we have both nMOS and pMOS transistors.
The intuition behind this design style is simple. First, you don’t want to have nMOS and pMOS transistors mixed up close to each other, because they need to be created on different types of substrate. So the natural style is to have a bunch of nMOS transistors together that pull the output one way for certain input values, and a bunch of pMOS transistors together that pull the output the other direction for the other input values. It turns out to work better to have the nMOS transistors pull down toward logic 0 and the pMOS transistors pull up toward logic 1. This is both for electrical reasons (nMOS conducts 0 better; pMOS conducts 1 better) and also to make it easy to get inverting gates.
The following diagram showing how to make an inverter (a NOT gate):
Such that we developed CMOS Technology by combination of Pull-up network of PMOS Transistors and Pull-down network of NMOS Transistors. All the CMOS gates are constructed using as shown below.
CMOS Constructed by, PMOS transistors in Pull-up network stage and NMOS transistors in Pull-down network stage.
OUTPUT going 1->0
The Pull-down NMOS transistors discharges the output capacitance.
OUTPUT going 0->1
The output capacitance is charged through Pull-up PMOS transistors.
MOSFETs transition states in CMOS Transistor:
CMOS logic is better logic than PMOS and NMOS implementations individually. Because PMOS transistors are great at transmitting a logic 0 to1 voltage without signal loss, NMOS transistors are great at transmitting a logic 1 to 0 voltage.
4.2 NAND GATE:
Constructed by, As shown below PMOS transistors in parallel and NMOS transistors in series.
OUTPUT going 1->0
The series NMOS transistors discharges the output capacitance.
OUTPUT going 0->1
The output capacitance is charged through parallel PMOS transistors.
Circuit diagram of NAND Gate:
Logic symbol of NAND Gate:
Truth table of NAND Gate:
A
B
OUTPUT
0
0
1
0
1
1
1
0
1
1
1
0
4.3 NOR GATE:
Constructed by, As shown NMOS transistors in parallel and PMOS transistors in series.
OUTPUT going 1->0
The parallel NMOS transistors discharges the output capacitance.
OUTPUT going 0->1
The output capacitance is charged through series PMOS transistors.
Circuit diagram of NOR Gate:
Logic symbol of NOR Gate:
Truth table of NOR Gate:
XOR GATE:
XOR is also called Exclusive OR gate or EOR gate. This is a digital logic gate, which is used to express the function of Exclusive Disjunction. Its behavior is similar to or gate with exclusive condition. Usually it is a 2-1 input output IC respectively.
An output HIGH (1) will be resulted if one, and only one of its 2 inputs is HIGH (1). Result of output LOW (0) both the inputs should be same either low or high. We can say EX-OR gate as “One or another, but not both”.
XOR gate is used to develop a binary addition. It gives the sum for given input bits. As shown above xor of 2 bits A and B gives its sum.
A xor B = A.B’ + A’.B
Circuit diagram of xor gate:
BASIC ADDER UNIT
Addition of two binary numbers is the most basic arithmetic operation i.e. two bits. A combinational circuit which can add only two bits is known as half adder. A full adder is one that adds more than two bits i.e. three bits. Full adder uses two adders in its implementation. In this study full adder is the basic addition employed in all adders.
HALF ADDER
Half is a basic adder circuit that can perform addition of two bits and gives the output of sum and carry. Half adder circuit uses an Exclusive-OR and AND gates for sum and carry outputs. XOR gate gives the sum output and carry output is given by the AND gate. X and Y are inputs S is sum and C0 is carry.
S = X.Y’ + X’.Y = X ƒ… Y
C = X.YIts schematic representation is as shown in the figure.
The truth table of half adder is as shown below.
X
Y
SUM
C0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
K-MAPPING of half adder circuit is given as shown below.
Sum, S = X ƒ… Y
Carry, C0 = X.Y
FULL-ADDER
Full adder can be formed by combining two half-adder circuits followed by the OR gate. It can perform the addition of three bits along with the carry input given as output from the previous one. The difference between half adder and full adder is that half adder cannot count more than two bits and cannot add the carry input which will be possible in full adder circuit. In this circuit, sum output is given by the XOR gate and the carry output is given by the AND gate followed by the OR gate. The block diagram of full adder circuit is as shown below.
FULLADDER
Sum S = X ƒ… Y ƒ… CI = (X ƒ… Y) ƒ… CI
Carry C0 = (X .Y) + (X ƒ… Y).CI
As shown in the above figure X, Y and CI are the adder inputs.
The truth table of the above circuit is as shown below.
X
Y
CI
SUM
C0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
By using K-mapping we will get SUM and CARRY as follows
Sum S,
Carry c0,
D – FLIP FLOP
D- Flip flop is used in many applications. RS flip flop is the fundamental building block for the D- flip flop. It has only one data input. That is connected to the input S of RS flip flop where as D is inversely connected to the R input.. D- Flip flop is also having second input for holding the data which is known as Enable, simply represented as EN. The enable input is AND-ed with the D- Flip flop. D- Flip flop holds the data according to the clock pulse.
It is constructed by using AND gates and NOR gates as shown in the below figure. D and EN are the inputs and Q and Q’ are outputs. The block diagram of the D-flip flop is as shown below.
D- Flip flop acts as temporary data storage in the 1- bit serial adder. Its storage capacity depends on the number of stages. The storage capacity of the D- flip flop in this serial adder is the total number bits (0 and 1) of digital data it can retain.
Its truth table is a shown below.
D
EN
Q
QN
0
Falling edge
0
X
0
Rising edge
0
1
1
Falling edge
Qprev
X
1
Rising edge
1
0
.
The wave forms are attached in the results.
CHAPTER 2
SERIAL ADDER
The process known as serial addition of binary numbers is well known in the digital and units capable of performing such serial binary addition ordinarily comprise a basic portion of more complex computation devices. In the past, such serial adders for binary numbers have employed vacuum tube circuitry for the most part and have accordingly been subject to the disadvantages that they are relatively in large size, fragile in configuration and are subject to operating failures. These factors raise serious questions of disposition of components and problems of maintenance. The present invention serves to obviate the foregoing difficulties and in essence provides a serial adder structure capable of performing full addition of binary numbers. It is accordingly an object of the present invention to provide an improved serial adder for use in digital systems.
The main aim of designing the bit serial adder is to perform one bit at a time, using the first bit operation results to influence the processing of subsequent bits. Here in this case the one bit serial adder is designed by using a D-flip flop and full adder. .
This circuit has two stages full adder stage for the addition of two bits that are entered serially and second stage is D-flip flop stage which temporarily stores the carry until the next stage is processed. The temporary storage of the carry in the D-flip flop depends on the clock pulse. Its design principle shows how the two inputs entered serially. These two inputs will be added by the full adder along with the carry which was temporarily stored by the flip-flop and gives us the sum output and carry output. This is a practical serial adder that is used to add a
stream of two bits addition. First it takes the Least Significant Bits (LSB) in addition. Its block diagram is as shown in the figure.
As shown in the above figure the inputs Xi and Yi are serially entered into the full adder along with the temporary carry from the D-flip flop i.e. Ci and gives the carry output Ci+1 and sum output Si.
Hence serial adder is simple and because of feedback looping bit delays are expected. It can be constructed with very low cost and it is the perfect adder at low speed operations.
Si = Ci ƒ… Yi ƒ… Xi
Ci + 1 = Yi . Ci + Xi . Ci + Xi . Yi = Ci . (Xi ƒ… Yi) + Xi . Yi
The above equations represent the Sum and Carry outputs using Boolean equations.
The construction of 1-bit serial adder is as shown in the figure. As shown in the figure the inputs X and Y are serially entered through the full adder along with the carry input which was the feedback output of full adder. In this circuit, sum output is given by the XOR gate and the carry output is given by the AND gate followed by the OR gate. D- Flip flop used in this circuit acts as a temporary storage of carry.
TRUTH TABLE
X
Y
C00
S
CO
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
0
0
1
This entire design process and simulation can be done by using the mentor graphics version 2005 software.
Chapter 3
Nand gate design of serial adder:
4.4 NAND gate is BETTER THAN NOR.
As PMOS in parallel and NMOS in series the resultant transition delay at NAND gate is lesser than delay of NOR gate architecture.
To make PMOS as fast as NMOS we need enlarge channel and P-regions, but that leads to large silicon layout, and more cost and power wastage. So At same speed NOR is always larger than NAND. So it makes NAND more efficient than NOR. W/L ratio of NAND gate is smaller than NOR gate.
If inputs for gates are more then, NAND will be very faster than NOR.
So we use sop implementation rather than pos.
XOR GATE USING NAND GATES
In PMOS holes flow very slowly when compared to the electrons in the NMOS technology. Hence NMOS is faster than PMOS transistor. In NOR gate PMOS transistors are connected in series and in NAND gate PMOS transistors are connected in parallel hence NAND gate is faster than the NOR gate. Now considering another case to make this one bit serial adder little bit faster compared to the normal one bit serial adder the XOR gate is constructed by using the NAND gates which works faster than the normal XOR gate. The reason for constructing this XOR gate is that in the core library we are using to design the entire circuit XOR gate internally contains an OR gate which usually reduces the performance of XOR gate. Its circuit diagram is as follows.
X
Y
OUT
0
0
0
0
1
1
1
0
1
1
1
0Its truth table is as shown below.
D- Flip Flop using nand gates:
D Flip-Flop is the most popular Flip-Flop. As its output takes the value of data ( D ) input when the positive edge of clock pulse. D Flip-flop can be interpreted as a primitive memory cell.
D Flip-flops are basically used as Shift registers. As a D Flip-flop can produce a output signal with a time period delay of given clock pulse for an input signal i.e., one bit shifted right to the input given signal. The principle of D flip-flop is it captures the signal at the moment the clock goes high, and subsequent changes of the data lines do not influence Q until the rise of next clock edge. thus it works as a edge triggering mode at clock signal rising.
D Flip-flop is constructed using NAND gates as shown above, where D and CLOCK are the inputs and Q and QN are the out puts.
X
Y
C00
S
CO
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
0
0
1
CHAPTER 3
SUBSTRACTOR
Up to now we have seen how simple logic gates perform binary addition. It is only logical to assume that the same circuit can also perform the binary subtraction. If we look at the possibilities involved in subtracting one bit number from another, we can quickly see that three of the four possible combinations are easy and straight forward. The fourth one involves a bit more.
0 – 0 = 0
1 – 0 = 1
1 – 1 = 0
0 – 1 = 1, with a borrow bit.
That borrow bit is just like a borrow in decimal subtraction: it subtracts from the next higher order of magnitude in the overall number. The truth table of this sub tractor circuit looks like as shown below.
This is an interesting result. The difference, X-Y, is still an exclusive-OR function, just as the sum for addition. The borrow is still an AND function, but is X’Y instead of XY.
Adder/Subtractor logic developed using NAND gate (lower from higher):
Addition is adding positive two bits. Subtraction is nothing but an addition where we add one positive bit to another negative bit. That means the second bit will be the positive number with negative polarity. We can convert positive binary to negative binary by its 2’s compliment.
2’s compliment is nothing but adding 1 bit to the LSB side of 1’s compliment.
1’s compliment is in any binary code if we swap bits by 1 bit with 0 bit and 0 bit with 1 bit. That is flip the binary code image.
1’s compliment can be generated using XOR logic. when we give one pin of XOR gate dedicated to positive as logic 1, and other pin connected to the input binary bit, then output of EXOR will be swapped by 1’s with 0’s and 0’s with 1’s. At the same time other advantage is if the dedicated input pin is given logic, then out put will be same as input binary code.
Such that in that whole circuit by changing selective pin as 0 logic it works as adder and by changing selective pin as 1 logic it works as subtractor’s 1’s compliment input.
Let we consider A + B it is a simple addition,
For
A – B = A + (- B) = A + (B 1’s compliment + 1)
= A + B 1’s compliment + 1
As shown above to find A – B we give the full adder inputs as a to A, b to B 1’s compliment and finally c in as positive logic 1. Thus adding 2 bits of A And B in this way we get A- B.
Above developed subtractor circuit subtracts lower value bit from higher value bit so in 0-1 condition its not valid.
ADDER TRUTH TABLE WHEN EN =0
EN
X
Y
C00
S
CO
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
SUBSTRACTOR TRUTH TABLE WHEN EN =1
EN
X
Y
C00
S
CO
1
0
0
1
0
0
1
0
1
1
X
X
1
1
0
1
1
0
1
1
1
1
0
1
IMPLEMENTATION
The entire process of designing and layout of the 1-bit serial adder circuit is done by using the mentor graphics version 2005. The required logic gates and flip flop has been taken from the core library. Once taking all the required components from the core library wiring has been done again using the core library. One wiring has been done the sheet has been saved and done the schematic check. Once the schematic check has been done successfully then the view point has been created. Once view point has been done successfully the circuit has been run for simulation. After having done the simulation successfully the output waveforms has been checked. This output waveforms results the working of the entire circuit design. Once we got the outputs exactly what we are looking for we then go for layout design. This layout design is also done by using the core library which is known as silicon layout. After finishing the layout we will check the overflow of the IC which we will get at the end of the process.
Conclusion:
In the project of One Bit Serial Adder we obtained the knowledge about the functionality of adders and developed a fast adder using NAND gate Logic. We even obtain the knowledge about CMOS technology and functionality of IC Gates. As we developed using NAND gate logic implementation the architecture of IC will be much faster and efficient.
From the obtained results of Serial adder waveforms and IC design by comparing the theoretical and practical values are verified each other. Such that I can conclude the developed IC’s are well functioning in any application era with a delay of 0.5921ns.
Finally I concluded that a 1-bit Serial adder is developed in Conventional, NAND gate architecture and Adder/Subtractor architectures IC design and layout of IC design obtained and verified without errors. Functional and Electric Characteristics studied similar to CMOS technology as they developed.
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