Computer organisation is a study of computer architecture that includes CPU, memory, registers and so on. Data processing takes place in a CPU of a computer.
A CPU consists of three major parts and they are as follows:
Arithmetic Logic Unit (ALU)
Control Unit
Register Set
ALU
ALU is a part of a computer processor that performs arithmetic and logical operations on data. Arithmetic operations are addition, subtraction, division and multiplication. Whereas, logical operation is comparing letters, numbers or special characters. To process data and obtain result, the ALU receives data from other elements of a computer system namely, control unit, registers, memory and Input/Output (I/O) register.
Control Unit
The control unit determines when instructions can be executed and what sequences of operations are required to execute each instruction.
Register Set
Register set is a small data storage area used by processor. General-Purpose Register (GPR), status register and other registers used by a program are called register set. The values stored in a register can be accessed more quickly than data stored in a memory system.
2.2 Instruction Code
An instruction code is a collection of bits that instruct a computer to perform a specific task. It consists of two parts such as operation code (opcode) and operand. The opcode indicates an operation to perform and the operand indicates data address or data itself over which an operation has to perform (Refer to Figure 2.1).
Figure 2.1: Instruction Code
The opcode of an instruction is stored in a computer memory. The control unit gets an instruction from memory and read opcode bits. When an instruction is to be executed by a computer, fetch operation is enabled first. It fetches the opcode bits of an instruction from memory. Then, the control unit issues a sequence of operations in internal computer registers.
2.3 Addressing Modes
Addressing mode is a method of providing access to the data that is stored in memory. Memory consists of words; each word has its own address and holds some data. Different ways of specifying data addresses are called the addressing modes.
Computer uses various addressing modes that accommodate either one or both provisions. These provisions are as follows:
To ensure programming versatility, the programmer is provided with facilities such as memory pointers, data indexing, counters for loop control and program relocation.
It reduces number of bits in the address field of an instruction.
Instruction format is modified to include the mode field. Mode field is used to locate the operands that are required for the operation (Refer to Figure 2.2).
Figure 2.2: Instruction Format with Mode Field
Instructions are classified based on the number of operands and they are as follows:
Three-Address Instructions
Two-Address Instructions
One-Address Instructions
Zero-Address Instructions
2.3.1 Three-Address Instructions
Three-address instruction is specified as ‘operation add-1, add-2, add-3’. In this form, add-1, add-2 and add-3 refers to a register or to a memory location.
Example: ADD R1, R2, R3
This instruction adds content of register R2 to content of register R3 and stores the result in register R1.
ADD A, B, C is an example of a three-address instruction that refers to memory locations. This instruction adds content of memory location B to content of memory location C and stores the result in memory location A.
2.3.2 Two-Address Instructions
Two-address instruction is specified as ‘operation add-1, add-2’. In this form, add-1 and add-2 refers to a register or to a memory location.
Example: ADD R1, R2
This instruction adds content of register R2 to content of register R1 and stores the results in register R1. In this operation, original content of register R1 gets replaced and register R2 remains unchanged. This instruction is similar to a three-address instruction of the form ADD R1, R1, R2.
ADD A, B is an example of a two-address instruction that refers to memory locations. This instruction adds content of memory location B to content of memory location A and the result overrides original content of memory location A.
2.3.3 One-Address Instructions
One-address instruction is specified as ‘operation add-1’. In this form, the instruction refers to a register called an accumulator.
Example: ADD R1
This instruction adds content of register R1 to content of accumulator and stores the results in the accumulator.
ADD B is an example of one-address instructions that refers to memory location. This instruction adds content of memory location B to content of accumulator and stores the result in the accumulator.
2.3.4 Zero-Address Instructions
Zero-address instructions do not include address field. In addition, zero-address instructions use stack operation. Stack is a data organisation mechanism. It is based on a Last In-First Out (LIFO) structure that is the last value stored in a stack will be removed first. Two specific operations can be performed on a stack such as push and pop operations. Push operation appends a new value on top of the stack and pop operation deletes top value from the stack.
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Push Operation – Stack Pointer (SP) is used to indicate stack location that can be addressed. In the stack push operation, top of SP is located at memory address 1003 in which value 6B needs to be stored (Refer to Figure 2.3). After storing this value, SP is incremented to address 1004 and it gets ready for the next push operation.
Figure 2.3: Stack Push Operation
Pop Operation – In the stack pop operation, top of SP is located at memory address 1004 (Refer to Figure 2.4). Pop is opposite to push operation. Hence, top of SP will be decremented to address 1003 and value 6B which is stored at this address will be removed.
Figure 2.4: Stack Pop Operation
Addressing modes are differentiated based on the address information of operands in an instruction. In each instruction, programmer has to specify three entities such as operation to be performed, address of source data and address of destination result.
Implicit Addressing Mode – In this mode, operands are specified implicitly in the definition of an instruction. For example, ‘CMA’ instruction complements the operand that is placed in an accumulator. In this case, accumulator is a source and a destination too.
Immediate Addressing Mode – In this mode, the instruction holds operand to be executed. These instructions are used for directly loading a register with a value. For example, ‘ADD 5’ will add 5 to content of an accumulator.
Register Direct Addressing Mode – In this mode, the operand value is stored in register and this register is displayed in an instruction. For example, ‘ADD R1’ will add content of register R1 to current content of accumulator.
Register Indirect Addressing Mode – In this mode, instruction specifies the address of CPU register. This register holds an address of memory location where the operand is stored. For example, ‘MOV CX, [BX]’ where BX register holds an address of main memory from which the operand is to be fetched and that operand is added to register CX.
2.4 Register
Register is a small amount of storage available in a CPU and its content can be accessed quickly. Registers are measured by number of bits it can hold, for example, an 8-bit register or a 32-bit register. The number of registers varies with CPU design approaches.
Some of the common registers are as follows:
Program Counter (PC) – It holds the address of next instruction that is to be executed by a CPU.
Instruction Register (IR) – It holds current instruction that is being executed by a CPU.
Memory Address Register (MAR) – It holds the address of memory where an operand is stored. By using this address, the data from memory location can be retrieved.
Memory Buffer Register (MBR) – It holds content of memory word while reading or writing into the memory. An instruction word placed in this
register is transferred to the IR. To transfer a word to main memory, it must be transferred through MBR.
Accumulator (AC) – It holds initial data to be operated on, intermediate results and final result of operations. The result of arithmetic operations is stored in an accumulator and from accumulator it is sent to memory storage through the MBR.
I/O Register – This register is used to communicate with the I/O devices. Input information is transferred to this register by an input device, as well as, all information that is to be sent to an output device is also stored in it.
2.5 Instruction Sets
An instruction includes opcode and one or more operands. Opcode specifies an operation to be performed on operand. An instruction set selected for a particular computer determines the way machine language programs are developed and executed.
The instruction sets can be differentiated in following ways:
Operand storage in a CPU
Number of explicit operands per instruction
Operand location
Operations
Type and size of operands
Main objective of processor designers is to improve performance. Performance depends upon amount of work that a processor is destined to do in a specific time. Different instructions perform different amount of work. To increase performance, either the processor should execute instructions in less time or should make each instruction it executes do more work.
There are two major instruction set design approaches namely, Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC).
RISC
RISC is designed to perform fewer instructions. It executes them at a higher speed by using less memory.
Some characteristics of RISC are as follows:
It has simple and basic instruction set.
It has fixed length instruction that can be fetched in a single operation.
It has single-cycle instruction execution.
A RISC processor has number of hardwired instructions.
It has fewer instructions and addressing modes.
It has efficient instruction pipeline.
CISC
CISC is designed to perform a large number of complex instructions set.
Some characteristics of CISC are as follows:
It has more instructions and addressing modes as compared to RISC.
It has variable-length instruction formats.
It has instructions that manipulate operands in memory.
Some instructions that perform specialised tasks are used occasionally.
A CISC processor executes microcode instructions.
An instruction set of a computer includes different types of instructions. These instructions are classified as follows:
Data Transfer Instructions
Data Manipulation Instructions
Program Control Instructions
2.5.1 Data Transfer Instructions
Data transfer instructions copies, moves or stores data from source to the destination. This move can be within processor register or in main memory without modifying the source content.
Table 2.1 shows a typical data transfer instructions.
Name
Mnemonic
Load
LD
Store
ST
Move
MOV
Exchange
XCH
Pop
POP
Push
PUSH
Output
OUT
Input
IN
Table 2.1: Typical Data Transfer Instructions
Some of the data transfer instructions are described as follows:
Load – This instruction is used to transfer data from memory location to processor register, which is usually an accumulator.
Store – This instruction is used to transfer data from processor register to memory location.
Move – This instruction is used to transfer data from register to memory or from memory to memory or from register to register.
Push and Pop – These instructions are used to transfer data between processor registers and stack.
Note: In an assembly language, mnemonic is a code which is usually from one to five letters. It represents an opcode followed by operands.
2.5.2 Data Manipulation Instructions
Data manipulation instructions perform binary operations on data stored in registers.
There are three bit manipulation instructions and they are as follows:
Clear – This instruction replaces the specified operand by zeros. The ‘AND’ operation is used to clear a bit or a selected group of bits of an operand. The ‘AND’ instruction is also called a mask because it masks or inserts zeros in a
selected group of bits of an operand.
Set – To set a particular string of bits, then each variable is ‘OR’ed with one.
Complement – To complement bits of an operand, a binary variable must be ‘XOR’ed with one.
Other data manipulation instructions are as follows:
Logical Shift Instructions
It is a bitwise operation that shifts all bits of operand to left or right. Every bit in an operand is moved by a given number of bit-positions and empty bit-positions are substituted with zeros. Logical shifts can be useful in performing multiplication or division of unsigned integers by powers of two.
Logical Shift Right (SHR) – In SHR, the Most Significant Bit (MSB) is replaced by a zero bit and the Least Significant Bit (LSB) is discarded (Refer to Figure 2.5).
Figure 2.5: Logical Shift Right
Logical Shift Left (SHL) – In SHL, the LSB is replaced by a zero bit and the MSB is discarded (Refer to Figure 2.6).
Figure 2.6: Logical Shift Left
Arithmetic Shift Instructions
Arithmetic shift instructions are called a signed shift. It is a bitwise operation that moves all bits of its operand. Every bit in an operand is moved by a given number of bit-positions and the vacant bit-positions are substituted. When shifting to left, an operation is similar to the SHL. Whereas, when shifting to right, the MSB which is usually a sign bit is substituted with copy of an original MSB.
Arithmetic Shift Right (SAR) – In SAR, MSB is a sign bit. It is replicated from an original MSB (Refer to Figure 2.7).
Figure 2.7: Arithmetic Shift Right
Arithmetic Shift Left (SAL) – In SAL, the LSB is replaced by a zero bit and the MSB is discarded (Refer to Figure 2.6).
Rotate With No Carry
Rotate instructions are circular and do not lose any of the bits through a right bit shift or left bit shift.
Rotate Right with No Carry (ROR) – In this instruction, all bits are shifted to right and the MSB is appended by the LSB (Refer to Figure 2.8).
Figure 2.8: Rotate Right with No Carry
Rotate Left with No Carry (ROL) – In this instruction, all bits are shifted to left and the LSB is appended by the MSB (Refer to Figure 2.9).
Figure 2.9: Rotate Left with No Carry
Rotate Through Carry
It is similar to the rotate no carry; only it includes Carry Flag (CF) during rotation.
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Rotate Right Through Carry (RCR) – This instruction shifts CF in the MSB and the LSB in CF (Refer to Figure 2.10).
Figure 2.10: Rotate Right through Carry
Rotate Left Through Carry (RCL) – This instruction shifts CF in the LSB and the MSB in CF (Refer to Figure 2.11).
Figure 2.11: Rotate Left through Carry
2.5.3 Program Control Instructions
Program control instructions modify the flow of control in a program. When these instructions are executed, it changes an address value in the PC and alters the flow of control in a program. This change in the PC value leads to break in the sequence of instruction execution.
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Table 2.2 shows some of the program control instructions.
Name
Mnemonic
Jump
JMP
Call
CALL
Return
RET
Branch
RR
Compare
CMP
Table 2.2: Program Control Instructions
Conditional Branch Instructions
Conditional branch instructions alter the flow of control in a program if a specified condition is met.
Subroutine Call and Return Instructions
When a main program calls a subroutine, the program control gets shifted to another location. The subroutine program will start from that location and return address will be stored in one of the registers in processor unit or in stack. Some of the subroutine instructions are call subroutine, jump to subroutine, branch to subroutine.
During the instruction execution, two operations are performed and they are as follows:
The address of a next instruction in the PC is stored in a temporary location so that subroutine knows where to return control after an execution.
Control is transferred to beginning of the subroutine.
Different computers use various temporary location for storing the return address. The most efficient way is to store it in a memory stack.
Program Interrupts
Program interrupt can cause a program to suspend itself temporarily to service an interrupt. After a program is interrupted and subroutine is executed, processor returns to original state where an interrupt had occurred.
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The states of CPU at the end of execute cycle are determined from content of different registers and they are as follows:
Content of PC
Content of all processor registers
Content of certain status conditions
Three types of interrupts are available namely, external interrupts, internal interrupts and software interrupts. External interrupts occur due to I/O devices, timing devices or any other external sources. Internal interrupts occur due to register overflow, attempt to divide by zero or stack overflow. External and internal interrupts are initiated in the hardware of CPU. A software interrupt is initiated by executing an instruction. Software interrupt is a special call instruction that acts as an interrupt instead of a call.
2.6 Instruction Execution and Micro-Operation
The program in computer system is executed by going through a cycle for each instruction. Each instruction cycle is subdivided into a sequence of subcycles such as fetch, decode (indirect), execute and an interrupt cycle. Each subcycle is in turn made up of a sequence of more fundamental operations called micro-operations. Figure 2.12 shows elements of a program execution and Figure 2.13 shows instruction cycles. A single micro-operation generally involves in transfer of data between registers or between registers and an external bus or it performs an ALU operation.
Figure 2.12: Elements of a Program Execution
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Figure 2.13: Instruction Cycles
Fetch Cycle – It is the time required for getting an instruction code from main memory to CPU. An instruction includes operand address or data. The fetch cycle gets an address stored in a PC which is memory address of next instruction to execute. CPU fetches an instruction from main memory and transfers it to IR. PC is then incremented to hold address of next instruction to fetch
Decode (Indirect) Cycle – It is used for interpreting an instruction that was fetched in the fetch cycle. If instruction has an indirect address, address will be read from main memory where data is stored. To process this data, it is fetched from main memory and placed in data registers.
Execute Cycle – It executes the instruction that was fetched and decoded.
Interrupt Cycle – After the completion of an execute cycle, the system checks for interrupt program. If there is no interrupt, then an instruction cycle returns to the fetch cycle to fetch next instruction. An interrupt can occur any time during the program execution.
When an interrupt occurs, following steps are performed by an operating system:
It suspends the execution of current instruction.
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It pushes an address of current instruction on the system stack.
It loads PC with address of the interrupt handler.
It executes an instruction in the interrupt handler.
Address of next instruction to be executed is obtained from popping the value of an address in a stack.
The suspended instruction then continues with its execution.
2.7 Basic Computer Organisation
Computers have instructions of different lengths. The number of address fields in an instruction format of a computer depends upon the internal organisation of its registers.
Most processor are organised in three types and they are as follows:
Single Accumulator Organisation
General Register Organisation
Stack Organisation
Single Accumulator Organisation
In this type of organisation, instructions are stored in one part of memory and data in another. The CPU has only one processor register that is accumulator.
Example: ADD X that is AC <- AC + M(X)
General Register Organisation
In this type of organisation, the computer requires three register address fields. Any of the registers can be used as source or destination. It is used by most modern computer processors.
Example: ADD R1, R2, R3 that is R1 <- R2 + R3
ADD R1, R2 that is R1 <- R1 + R2
Stack Organisation
In this type of organisation, the CPU uses stack memory. Push and Pop operation of a stack requires an address field.
Example: PUSH X
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2.8 Chapter Review Questions
Which of the following shift operations divide a signed binary number by two?
(A)
Logical shift left
(C)
Arithmetic shift left
(B)
Logical shift right
(D)
Arithmetic shift right
PUSH is ____-address instruction.
(A)
Zero
(C)
Two
(B)
One
(D)
Three
Which of the following addressing mode includes the operand in an instruction itself?
(A)
Direct addressing mode
(C)
Implicit addressing mode
(B)
Immediate addressing mode
(D)
Register addressing mode
Which of the following is based on a LIFO structure?
(A)
Program counter
(C)
Stack
(B)
Register
(D)
None of these
Which of the following register holds the address of the next instruction to be executed?
(A)
Program counter
(C)
Accumulator
(B)
Instruction register
(D)
Memory buffer register
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Which of the following register holds the current instruction that is being executed by the CPU?
(A)
Accumulator
(C)
Program counter
(B)
Instruction register
(D)
Memory buffer register
Which register holds the address of active memory location?
(A)
Program counter
(C)
Memory address register
(B)
Accumulator
(D)
Instruction register
_____ is designed to perform a fewer instructions.
(A)
Memory
(C)
RISC
(B)
CPU
(D)
CISC
Which of the following is not a characteristic of CISC?
(A)
Fewer number of instructions
(C)
Variable length instruction formats
(B)
Large number of instructions
(D)
Larger number of addressing modes
To complement bits of an operand, a binary variable must be ____ with one.
(A)
AND
(C)
XOR
(B)
OR
(D)
NAND
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2.8.1 Answers
1.
D
6.
B
2.
A
7.
C
3.
B
8.
C
4.
C
9.
A
5.
A
10.
C
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Summary
In this chapter, Computer Organisation, you learnt about:An instruction code that consists of opcode and operand. Different types of addressing modes.Different types of registers.Instruction sets and its classification.Different instruction cycles such as fetch, decode, execute and interrupt cycle.Basic computer organisation that includes single accumulator, general register and stack organisation.
Summary
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The foundation of every state is the education of its youth
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